The Lark Board evaluation board has been customized based on the three core resources of the SoC, namely traditional FPGA universal IO and logic, traditional ARM universal IO, controller, and high-speed differential transceiver. It provides onboard USB Blaster II JTAG online debugging function, TF card and eMMC startup, HPS and FPGA exclusive 1GB DDR3 memory, SDI high-definition input and output, VGA and HDMI high-definition display, small and medium-sized LCD touch screen interface, high bandwidth analog front-end, and ADC sampling Rich expansion interfaces and hardware resources such as 10/100/1000M Ethernet, USBx4 interface, digital camera interface, PCIEX1/X4 interface, RTC, HPS, and FPGA partial expansion. The following is the Lark Board system diagram, which clearly demonstrates how the evaluation board can explore the various functions of Cyclone V.
Let's take a closer look at each of the interfaces and hardware resources on the Lark Board, and see how it allows the Cyclone V SoC to fully unleash itself on this specially designed stage.
1. On board USB Blaster II
JTAG and USB Blaster II are basic Debugger for FPGA development. As a strategic partner of Altera, Embest has been authorized by Altera to use the online USB Blaster II on the Lark Board, improving the efficiency and reliability of FPGA debugging, saving users the trouble of purchasing an external Blaster, and also preventing the burning of the board caused by users forgetting to turn off the power due to hot swapping. In addition, the onboard USB Blaster II can support Quartus II and ARM DS-5 development environments.
2. Support TF card and eMMC startup-
The Lark Board comes with a TF Card socket and 4GB eMMC, and users can choose to boot from either eMMC or TF Card.
3. On board DDR3 memory
The SoC on the Lark Board integrates a hard core DDR controller in the FPGA and HPS sections, with two DDR3 particles (1GB each) externally connected. HPS and FPGA can access each other through internal bridging, with a maximum access space of 1GB and speeds up to 800MHz (1600Mbps).
4. SDI high-definition input and output
By configuring the built-in SDI transceiver of SoC, as well as the integrated LMH0303 cable driver and LMH0384 equalizer on the board, the Lark Board can use SMB coaxial lines to connect with high-definition IP Camera or DVR, achieving applications in security monitoring, medical imaging, automotive safety, and other areas.
5. VGA and HDMI
Lark Board integrates CH7033B HDTV/VGA/DVI display coding chip, has flexible Image scaling engine and simple digital audio configuration interface. In terms of display, it supports 1080 HDMI output, and VGA monitors can support a maximum resolution of 1920x1080. In terms of audio, it supports SPDIF and dual channel I2S audio inputs. The high fidelity audio decoding engine has a sampling rate of up to 192k/2ch, and supports PCB encoded data and Dolby/DTS compressed digital audio.
6. LCD touch screen interface
The 50Pin LCD touch screen interface on the Lark Board can support up to 24 bits of color data, while integrating touch screen control chips to easily convert coordinate data to standard SPI protocol data.
7. LNA (Low-noise amplifier) and ADC sampling
The Lark Board integrates a dual channel 3.3GHz RF/IF differential amplifier and a 12 bit 105MSPS ADC, enabling amplification, filtering, sampling, and other processing of RF and IF analog signals. Users can develop various data acquisition, analysis and processing systems, such as sampling oscilloscope, Software-defined radio base station, analog/digital TV reception, GPS/radar/sonar reception and processing systems, based on this prototype and the powerful computing and image processing capabilities of HPS&FPGA.
8. 10/100/1000 Mbps Ethernet
Lark Board integrates AR8035 single port 10/100/1000Mbps Ethernet controller, supporting MAC side RGMII interface; Provide low-cost and low-power network solutions.
9. USB PHY and Hub
The Lark Board includes a USB3320 high-speed USB2.0 physical layer transceiver and a USB2514 USB Hub, supporting up to 4 USB interfaces, making it easy to implement the Host/Slave/OTG functions included in the USB protocol, as well as high-speed, full speed, and low-speed transmission modes.
10. Digital camera interface
The Lark Board includes a 30Pin digital camera interface that can be connected to the camera through an FPC (flexible circuit board). Supports up to 12 digits of digital image input data.
11. PCI-E X1/X4 interface
The Lark Board includes PCI-E X1/X4 expansion slots, which can easily support various PCI-E expansion application cards by configuring the FPGA hard core.
12. RTC clock
The Lark Board includes the DS3231 clock chip, which can be connected to a 3V button lithium battery through the battery base on the board to achieve clock management after system power failure.
13. HPS (Hard Core Processor System) Partial IO Pin Expansion
HPS IO pins that are not directly utilized on the board or have reuse significance are led out through standard 40Pin sockets, facilitating users to expand and customize functions according to their own applications. Users can easily use HPS integrated QSPI, SPI, I2C, UART, and GPIO controllers.
14. FPGA partial IO pin expansion
The IO pins of the FPGA that are not directly utilized on the board are led out through another standard 40Pin socket, making it convenient for users to expand and customize functions according to their own applications. Users can easily achieve customized applications of various high bandwidth functions by configuring the hard core and logical resources within the FPGA. The supported transmission protocols include LVDS, RSDS, SLVS, Mini LVDS, etc.
